`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/10/02 12:11:27
// Design Name: 
// Module Name: tb_fc_1_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_fc_1_top();

    reg         clk;
    reg         rst_n_fc;
    reg         start;
    wire        done_o;
    wire [31:0] fc_output_data_monitor;
    wire        fc_output_wren_monitor;
    fc_1_top u_fc_top(
        .clk(clk),
        .rst_n_fc(rst_n_fc),
        .start(start),
        .done_o(done_o),
        .fc_output_data_monitor(fc_output_data_monitor),
        .fc_output_wren_monitor(fc_output_wren_monitor)
    );

    integer file_handle;
    initial begin
        file_handle = $fopen("D:/Verilog/FullConnectionLayer/output1.txt", "w");
    end

    always @(negedge clk) begin    //在clk的下降沿切中fc_output_wren_monitor
        if (fc_output_wren_monitor) begin
            $fwrite(file_handle, "%d\n", fc_output_data_monitor);
        end
    end

    initial begin
        forever #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        rst_n_fc = 0;
        start = 0;
        #20 rst_n_fc = 1;
        #10 start = 1;
    end

    always @(posedge clk) begin
        if(done_o) begin
            start = 0;
            $finish;
        end      
    end

endmodule
